1. Field of the Invention
The present invention generally relates to semiconductor devices and manufacturing methods of the same, and more specifically, to a semiconductor device having a projection electrode (bump) for outside connection and an organic insulation film and a manufacturing method of the same.
2. Description of the Related Art
Recently, a flip chip connection structure using a projection electrode for outside connection, called a bump, has been widely applied for high density mounting of a package and a semiconductor element.
In a case where solder is selected as a material of such a bump, the bump can be formed by a plating method or a printing method.
A barrier metal layer is formed on the electrode layer by using an electrolytic plating method in order to prevent the solder from being diffused on the semiconductor element, and the soldering bump is formed on the barrier metal layer by a plating method. See Japanese Laid-Open Patent Application Publications No. 2004-200420 and No. 9-191012, for example.
In this case, a surface of the semiconductor element is covered with an organic insulation film such as polyimide for device protection. The surface of the electrode layer is also selectively covered with the organic insulation film.
A manufacturing process of the bump by using the relating art plating method in a manufacturing process of the semiconductor device is shown in FIG. 1.
In a bump forming process by using the related art plating method, first, as shown in FIG. 1-(a), a wiring layer made of silicon (Si) and an electrode layer (electrode pad) 3 are provided on an upper surface, namely a circuit element forming surface, of a semiconductor substrate 1 made of silicon (Si) via an insulation film (insulation layer) made of silicon oxide, for example.
An upper part of the semiconductor substrate 1 including the wiring layer and the electrode layer 3 is covered with an inorganic insulation film (passivation film) 2 made of silicon nitride (SiN) or the like.
In addition, an organic insulation film 4 such as a polyimide resin layer or the like is provided on the inorganic insulation film 2. The organic insulation film 4 is formed for surface protection of the semiconductor element and for easing stress concentrated on a base of the bump 9 when the semiconductor element is mounted on a wiring board 11 (See FIG. 3).
An opening is formed in the inorganic insulation film 2 and the organic insulation film 4 as corresponding to an expected forming position on the electrode layer 3 of the soldering bump 9 so that a pad is exposed.
Illustration of an active element such as a transistor, and a passive element such as resistor element or capacity element formed on the semiconductor substrate 1, an isolation area for insulation-isolating between these elements, an interlayer insulation layer, an inter-element mutual wiring layer, or the like is omitted in FIG. 1.
Next, as shown in FIG. 1-(b), a power supply layer 5 as a plating electrode is formed, by sputtering method, on whole surfaces of the electrode layer (electrode pad) 3 and the organic insulation film 4 on the semiconductor substrate 1.
Next, a photo resist layer 6 is applied on the power supply layer 5 by a spin coating method and exposure, developing and curing processes are performed, so that, as shown in FIG. 1-(c), the opening corresponding to the expected forming position on the electrode layer 3 of the soldering bump 9 is formed in the photo resist layer 6.
Next, an electrolytic plating process is performed, so that, as shown in FIG. 1-(d), a barrier metal layer 7 is formed in the opening in the photo resist layer 6 so that the diffusion of solder in the soldering layer 9 into the electrode layer is prevented.
Next, an electrolytic plating process is made by using the photo resist layer 6 as a mask, so that, as shown in FIG. 1-(e), a tin-silver (Sn—Ag) soldering layer 9 is formed on the barrier metal layer 7. At this time, the soldering layer 9 is formed so as to extend on the photo resist layer 6.
Next, as shown in FIG. 1-(f), the photo resist layer 6 is removed by using release liquid. Furthermore, an unnecessary part of the power supply layer 5 is removed by wet etching wherein the soldering layer 9 is used as an etching mask.
After that, the soldering layer 9 is made molten by reflow heating so that, as shown in FIG. 1-(g), the soldering layer 9 is formed in a substantially spherical shape. In other words, a spherical-shaped soldering bump (soldering ball) 9 is formed on the electrode layer 3 of the semiconductor substrate 1.
In a case where the bump is manufactured by using the printing method, after the barrier metal layer 7 is selectively formed in the opening in the photo resist 6 shown in FIG. 1-(d), as shown in FIG. 2-(a), the photo resist layer 6 is removed by using the release liquid and the wet etching process using the etching liquid is applied to the power supply layer 5.
After that, as shown in FIG. 2-(b), a pattern (not illustrated) for printing is made so that the tin-silver (Sn—Ag) soldering layer 9 is formed on the barrier metal layer 7, and the soldering plating layer 9 is made molten by reflow heating. As a result of this, as shown in FIG. 1-(g), the spherical-shaped soldering bump (soldering ball) 9 is formed on the electrode layer 3 of the semiconductor substrate 1.
An example of a method of mounting the semiconductor element 10 where the bump 9 made of tin-silver (Sn—Ag) soldering is formed on the semiconductor substrate 1, on the printed board 11 is shown in FIG. 3.
As shown in FIG. 3-(a), the semiconductor element 10 where the bump 9 is formed on the semiconductor substrate 1 is mounted on the printed board 11 by a flip chip bonding method. In other words, where the surface of the semiconductor element 10 has the bump 9 formed facing downward, the semiconductor element 10 is mounted on an upper surface, namely a wiring surface of the printed board 11. Here, ball bumps 12 for outside input/output are formed on a lower surface of the printed board 11
Next, as shown in FIG. 3-(b), in order to improve connection reliability, underfill 13 is applied between the semiconductor element 10 and the printed board 11 and cured, so that connection between the semiconductor element 10 and the printed board 11 is reinforced.
Last, as shown in FIG. 3-(c), a passive element 14 such as a condenser or the like is provided in the periphery of the semiconductor element 10 on the printed board 11 and a heat radiation plate 15 for radiating heat generated by the semiconductor element 10 is provided at an upper part of the semiconductor element 10, so that the semiconductor device is formed.
In the meantime, details of forming of the power supply layer 5 on the electrode layer (electrode pad) 3 and the organic insulation film 4 discussed with reference to FIG. 1-(b) and details of the wet etching process for the power supply layer 5 discussed with reference to FIG. 1-(f) and FIG. 2-(a) are discussed with reference to FIG. 4 through FIG. 6.
Here, FIG. 4 is a view for explaining an electrode layer (electrode pad) and a power supply layer on an organic insulating protection film. FIG. 5 is a view for explaining the status of a surface of the organic insulating protection film in processes shown in FIG. 4. FIG. 6 is a view for explaining the status of a surface of the organic insulating protection film in a process for removing the power supply layer by a wet etching process.
In order to form the power supply layer 5 on the electrode layer (electrode pad) 3 and the organic insulation film 4, first, as shown in FIG. 4-(a), a dry etching (RF etching) process is applied to the whole surfaces of the electrode layer (electrode pad) 3 and the organic insulation film 4 by using argon (Ar) gas so that a natural oxide film on the surface of the electrode layer (electrode pad) 3 is removed.
By such a dry etching process, as shown in FIG. 5-(a), a modified layer is generated on a surface layer of the organic insulation film 4. The etching amount of the surface of the organic insulation film 4 at this time is small and the maximum surface roughness of the organic insulation film 4 is approximately 4 nm. Therefore, the surface roughness of the organic insulation film 4 is not dramatically changed by this process.
Next, a metal forming the power supply layer 5 is deposited on the surface of the organic insulation film 4 including the modified layer 20 by sputtering.
More specifically, as shown in FIG. 4-(b), a titanium (Ti) layer 5-1 is formed on a surface of the organic insulation film 4 including the modified layer 20 by sputtering. By such a sputtering, as shown in FIG. 5-(b), titanium is embedded in the surface of the modified layer 20.
Next, as shown in FIG. 4-(c), a copper (Cu) film 5-2 is formed on the surface of the titanium (Ti) film by sputtering. At this time, as shown in FIG. 5-(c), since the copper film 5-2 is deposited on the titanium film 5-1, the copper film 5-2 does not directly come in contact with the organic insulation film 4 and therefore does not influence the surface of the organic insulation film 4.
In the process shown in FIG. 1-(f) in the case of the plating method or in the process shown in FIG. 2-(a) in the case of the printing method, the power supply layer 5 (the titanium film 5-1 and the copper film 5-2) formed on the organic insulation film 4 is removed by the wet etching process.
Next, with reference to FIG. 6, the status of the surface of the organic insulation film 4 in the process whereby the power supply layer 5 is removed by the wet etching process is discussed.
Where the copper film 5-2 is deposited on the titanium film 5-1 as shown in FIG. 6-(a), first, the copper film 5-2 is removed by wet etching as shown in FIG. 6-(b). Since the copper film 5-2 is deposited on the titanium film 5-1, it is possible to easily remove the copper film 5-2.
Next, as shown in FIG. 6-(c), the titanium film 5-1 deposited on the modified layer 20 is removed by wet etching. While the titanium film 5-1 provided on the surface of the modified layer 20 is easily removed, titanium embedded in the surface of the modified layer 20 remains even after the titanium film 5-1 provided on the surface of the modified layer 20 is removed.
FIG. 7 is a view of the soldering bump 9 formed on the semiconductor element 10 of the semiconductor device manufactured by the related art manufacturing method including the above-discussed processes. FIG. 7-(b) is an expanded view of a part surrounded by a broken line in FIG. 7-(a).
Referring to FIG. 7, in the semiconductor element 10 manufactured by the above-discussed processes, the titanium film 5-1, the copper film 5-2 and the barrier metal layer 7 are formed on the organic insulation film 4 in this order. The bump 9 is formed on the barrier metal layer 7.
Titanium 5-1 embedded in the surface of the organic insulation film 4 and remaining as a metal residue is normally not observed by a metal microscope, an electron microscope, or the like. However, approximately 10 atm % of this titanium 5-1, as a maximum, is detected by analysis using X-ray Photoelectron Spectroscopy (XPS). The surface roughness of the organic insulation film 4 is approximately 4 nm as a maximum, which is substantially equal to the surface roughness of the organic insulation film 4 formed on the inorganic insulation film 2 shown in FIG. 1-(a).
Thus, in the semiconductor device manufactured by the related art method, the titanium 5-1 forming the power supply layer 5 remains embedded in the surface of the organic insulation film 4 of the semiconductor element 10 as the metal residue.
However, such a metal residue obstructs adhesion between the organic insulation film 4 and the underfill 13 (See FIG. 3) filling in between the semiconductor element 10 and the printed board 11 for reinforcing the connection between the semiconductor element 10 and the printed board 11. As a result, the reliability of the connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11 may be degraded.
On the other hand, as discussed above, the surface roughness of the organic insulation film 4 is approximately 4 nm as a maximum, which is substantially equal to the surface roughness of the organic insulation film 4 formed on the inorganic insulation film 2. Therefore, the surface roughness of the organic insulation film 4 is too small to obtain sufficient adhesion with the underfill 13.
Accordingly, the reliability of the connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11 may be degraded.
Thus, in order to ensure a reliable connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11, it is necessary to both remove the metal residue remaining embedded in the surface of the organic insulation film 4 and make the surface roughness of the organic insulation film 4 large so that sufficient adhesion with the underfill 13 can be obtained.
If the organic insulation film 4 in the vicinity of the bump 9 is removed for the above-mentioned purpose, when the semiconductor element 10 is mounted on the printed board 11, stress is concentrated on the organic insulation film 4 in the vicinity of the bump 9. As a result, cracks may be generated in this part, and therefore the reliability of the connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11 may be degraded.